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44vhdl
- 44个vhdl实例 注1： 含有不可综合语句，请自行修改 注2： 一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化-44 VHDL examples Note 1 : Includes an integrated statement, the initiative to revise Note 2 : Some PLD only allows I / O exte
dpram_fpga
- 这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
my_ramlib_06
- 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL descr iption, such as FIFO, Dual Port RAM, etc.
vhdl_ad0809_arm
- 本程序是用VHDL语言写的，包括AD0809，双口RAM等程序。已经调试过-this program is written in VHDL, including the AD0809, dual-port RAM, and other procedures. Debugging has been too
SimpleRAMModel
- 一个SIMPLE RAM ACCESS的VHDL很经典的例子，我老师的作品。-a SIMPLE RAM ACCESS VHDL classic example of my teacher's work.
VHDLRAM
- 介绍vhdl硬件描述语言的特点及设计思想，运用vhdl硬件描述语言实现计算机原理实验中RAM存储器的设计方法，重点描述了对传统计算机组成原理实验中移植到基于CPLD平台的思想-introduced vhdl hardware descr iption language features and design ideas, vhdl use hardware descr iption language computer science experiments RAM memory design,
DDR_SDRAM_Controller
- DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
ram4
- VHDL 程序实现的 ram4 是一个四输入，四输出的 ram模块，在lmp_ram_dp 的dual ram 基础上扩展而成 完成一次操作需要5个时钟周期-VHDL ram4 the program is a four input and four output ram module, lmp_ram_dp in the dual ram from the expansion on the basis of a complete operational needs five clock
DDS_sin
- 用VHDL语言实现DDS直接数字频率合成器的设计，采用正弦RAM表，可实现频率可控的正弦数字信号，编译、仿真通过。-VHDL DDS Direct Digital Frequency Synthesizer Design using sinusoidal RAM table achieve controllable frequency sinusoidal digital signal, compile, through simulation.
RAM_VHDL_34
- RAM之VHDL描述 RAM之VHDL描述-RAM's VHDL descr iption RAM's VHDL descr iption RAM's VH DL described in VHDL's RAM
ram
- vhdl code for simple ram block
ram
- This file is about create memory in ISE by VHDL language.
20_RAM
- RAM vhdl source code
ram
- 基于VHDL的教学实验机ram芯片连续读写-RAM chip based on VHDL continuous read and write
RAM2048X8
- you can add this code to your project if you need RAM2048X8
ram2114
- 一个简单的2114存储器，哈工大计算机组成原理(intel 2114 ram, from hit computer)
vhdl_ram
- Fast generic RAM model
Block_RAM
- ditributed ram in fpga and block ram in fpga
a simple 4_4 RAM module
- a simple 4*4 RAM module implementing in vhdl
vhdl实现异步fifo
- 使用vhdl实现异步fifo功能，不占用ram资源，仅占用少量LE资源，且读写计数进行了格雷码转换，使用安全